sh_cam Project Status | |||
Project File: | sh_cam.ise | Current State: | Programming File Generated |
Module Name: | top_level |
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No Errors |
Target Device: | xc3s500e-4pq208 |
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83 Warnings |
Product Version: | ISE 10.1 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
sh_cam Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 340 | 9,312 | 3% | ||
Number of 4 input LUTs | 382 | 9,312 | 4% | ||
Logic Distribution | |||||
Number of occupied Slices | 323 | 4,656 | 6% | ||
Number of Slices containing only related logic | 323 | 323 | 100% | ||
Number of Slices containing unrelated logic | 0 | 323 | 0% | ||
Total Number of 4 input LUTs | 428 | 9,312 | 4% | ||
Number used as logic | 382 | ||||
Number used as a route-thru | 46 | ||||
Number of bonded IOBs | |||||
Number of bonded | 148 | 158 | 93% | ||
IOB Flip Flops | 1 | ||||
Number of BUFGMUXs | 2 | 24 | 8% | ||
Number of DCMs | 1 | 4 | 25% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | “y 5 23 18:57:25 2009 | 0 | 78 Warnings | 1 Info | |
Translation Report | Current | “y 5 23 18:57:30 2009 | 0 | 0 | 0 | |
Map Report | Current | “y 5 23 18:57:35 2009 | 0 | 2 Warnings | 3 Infos | |
Place and Route Report | Current | “y 5 23 18:57:49 2009 | 0 | 3 Warnings | 2 Infos | |
Static Timing Report | Current | “y 5 23 18:57:52 2009 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | “y 5 23 18:57:58 2009 | 0 | 1 Warning | 0 |