sh_cam Project Status
Project File: sh_cam.ise Current State: Programming File Generated
Module Name: top_level
  • Errors:
No Errors
Target Device: xc3s500e-4pq208
  • Warnings:
83 Warnings
Product Version: ISE 10.1 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
sh_cam Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 340 9,312 3%  
Number of 4 input LUTs 382 9,312 4%  
Logic Distribution     
Number of occupied Slices 323 4,656 6%  
    Number of Slices containing only related logic 323 323 100%  
    Number of Slices containing unrelated logic 0 323 0%  
Total Number of 4 input LUTs 428 9,312 4%  
    Number used as logic 382      
    Number used as a route-thru 46      
Number of bonded IOBs
Number of bonded 148 158 93%  
    IOB Flip Flops 1      
Number of BUFGMUXs 2 24 8%  
Number of DCMs 1 4 25%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent“y 5 23 18:57:25 2009078 Warnings1 Info
Translation ReportCurrent“y 5 23 18:57:30 2009000
Map ReportCurrent“y 5 23 18:57:35 200902 Warnings3 Infos
Place and Route ReportCurrent“y 5 23 18:57:49 200903 Warnings2 Infos
Static Timing ReportCurrent“y 5 23 18:57:52 2009003 Infos
Bitgen ReportCurrent“y 5 23 18:57:58 200901 Warning0

Date Generated: 05/24/2009 - 18:55:56
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