spectrumanalyzer Project Status
Project File: spectrumanalyzer.ise Current State: Programming File Generated
Module Name: analyzer_root
  • Errors:
No Errors
Target Device: xc3s400-4tq144
  • Warnings:
49 Warnings
Product Version: ISE 10.1.03 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
spectrumanalyzer Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 1,141 7,168 15%  
Number of 4 input LUTs 1,037 7,168 14%  
Logic Distribution     
Number of occupied Slices 924 3,584 25%  
    Number of Slices containing only related logic 924 924 100%  
    Number of Slices containing unrelated logic 0 924 0%  
Total Number of 4 input LUTs 1,126 7,168 15%  
    Number used as logic 831      
    Number used as a route-thru 89      
    Number used as Shift registers 206      
Number of bonded IOBs
Number of bonded 29 97 29%  
    IOB Flip Flops 9      
Number of RAMB16s 8 16 50%  
Number of MULT18X18s 7 16 43%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 1 4 25%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent金 1 30 14:49:51 2009015 Warnings5 Infos
Translation ReportCurrent金 1 30 14:50:07 2009027 Warnings0
Map ReportCurrent金 1 30 14:50:20 200906 Warnings2 Infos
Place and Route ReportCurrent金 1 30 14:50:51 200901 Warning0
Static Timing ReportCurrent金 1 30 14:50:59 2009002 Infos
Bitgen ReportCurrent金 1 30 14:51:11 200902 Warnings2 Infos

Date Generated: 01/30/2009 - 14:53:29
<