FG Project Status
Project File: FG.ise Current State: Programming File Generated
Module Name: top
  • Errors:
No Errors
Target Device: xc3s700a-5fg484
  • Warnings:
28 Warnings
Product Version: ISE 10.1 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
FG Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 84 11,776 1%  
Number of 4 input LUTs 17 11,776 1%  
Logic Distribution     
Number of occupied Slices 43 5,888 1%  
    Number of Slices containing only related logic 43 43 100%  
    Number of Slices containing unrelated logic 0 43 0%  
Total Number of 4 input LUTs 54 11,776 1%  
    Number used as logic 17      
    Number used as a route-thru 37      
Number of bonded IOBs 19 372 5%  
Number of BUFGMUXs 1 24 4%  
Number of RAMB16BWEs 6 20 30%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent日 12 14 10:25:19 2008010 Warnings7 Infos
Translation ReportCurrent日 12 14 10:25:30 2008000
Map ReportCurrent日 12 14 10:25:44 2008018 Warnings2 Infos
Place and Route ReportCurrent日 12 14 10:26:15 2008002 Infos
Static Timing ReportCurrent日 12 14 10:26:26 2008003 Infos
Bitgen ReportCurrent日 12 14 10:26:42 2008018 Warnings0

Date Generated: 12/14/2008 - 12:41:39
<