cic Project Status | |||
Project File: | APB3.xise | Parser Errors: | No Errors |
Module Name: | cic | Implementation State: | New |
Target Device: | xc6slx9-3tqg144 |
|
|
Product Version: | ISE 13.1 |
|
|
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: |
|
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | ‹à 11 18 09:45:55 2011 | |
SmartXplorer Report | Current | “y 8 20 20:53:05 2011 | |
WebTalk Report | Current | “y 3 17 10:30:23 2012 | |
WebTalk Log File | Current | “y 3 17 10:30:30 2012 |