Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2552052
date_generatedThu Aug 22 00:50:25 2019 os_platformWIN64
product_versionVivado v2019.1 (64-bit) project_idbeddd6f81e72487ab993d50a15828c86
project_iteration2 random_idaba8bab3fd6a5754a4b7e79dcd29ec99
registration_idaba8bab3fd6a5754a4b7e79dcd29ec99 route_designTRUE
target_devicexc7a35ti target_familyartix7
target_packagecsg324 target_speed-1L
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6950X CPU @ 3.00GHz cpu_speed3000 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram137.000 GB total_processors1

vivado_usage
gui_handlers
basedialog_apply=1 basedialog_cancel=1 basedialog_ok=4 basedialog_yes=4
cmdmsgdialog_ok=1 constraintschooserpanel_add_files=2 filesetpanel_file_set_panel_tree=2 flownavigatortreepanel_flow_navigator_tree=6
fpgachooser_family=2 fpgachooser_fpga_table=2 fpgachooser_package=2 fpgachooser_speed=2
gettingstartedview_create_new_project=1 gettingstartedview_open_project=1 mainmenumgr_file=4 mainmenumgr_project=2
msgtreepanel_message_view_tree=4 pacommandnames_add_sources=1 pacommandnames_auto_connect_target=1 pacommandnames_bitstream_settings=2
pacommandnames_new_project=1 pacommandnames_open_hardware_manager=1 paviews_project_summary=1 programdebugtab_open_target=1
programdebugtab_program_device=1 programfpgadialog_program=1 programfpgadialog_specify_bitstream_file=1 projectnamechooser_choose_project_location=2
projectnamechooser_project_name=1 rungadget_show_error=2 rungadget_show_error_and_critical_warning_messages=1 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=8
java_command_handlers
addsources=1 autoconnecttarget=1 launchprogramfpga=1 newproject=2
openhardwaremanager=1 openproject=1 runbitgen=4 showview=5
toolssettings=2
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=12 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=2 carry4=92 fdce=16 fdre=1308
fdse=16 gnd=12 ibuf=7 lut1=130
lut2=148 lut3=239 lut4=224 lut5=245
lut6=1990 muxf7=616 muxf8=305 obuf=8
ramb18e1=1 ramb36e1=15 ramd32=16 ramd64e=6144
vcc=11
pre_unisim_transformation
bufg=2 carry4=92 fdce=16 fdre=1308
fdse=16 gnd=12 ibuf=7 lut1=130
lut2=148 lut3=239 lut4=224 lut5=245
lut6=1990 muxf7=616 muxf8=305 obuf=8
ram32x1d=8 ram64m=1536 ramb18e1=1 ramb36e1=15
vcc=11

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=16 bram_ports_newly_gated=0 bram_ports_total=32 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=1340 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
hls_ip_2019_1/1
core_container=NA hls_input_arch=others hls_input_clock=8.000000 hls_input_fixed=0
hls_input_float=0 hls_input_part=xc7a35ti-csg324-1L hls_input_type=c hls_syn_clock=6.190000
hls_syn_dsp=0 hls_syn_ff=208 hls_syn_lat=-1 hls_syn_lut=1774
hls_syn_mem=1 hls_syn_tpt=none hls_version=2019_1 iptotal=1
hls_ip_2019_1/2
core_container=NA hls_input_arch=others hls_input_clock=8.000000 hls_input_fixed=0
hls_input_float=0 hls_input_part=xc7a35ti-csg324-1L hls_input_type=c hls_syn_clock=6.483500
hls_syn_dsp=0 hls_syn_ff=400 hls_syn_lat=-1 hls_syn_lut=1588
hls_syn_mem=0 hls_syn_tpt=none hls_version=2019_1 iptotal=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
lutar-1=1 timing-17=1000

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.006057 clocks=0.000399
confidence_level_clock_activity=Low confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.062205 die=xc7a35ticsg324-1L dsp_output_toggle=12.500000 dynamic=0.024314
effective_thetaja=4.8 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.001814 input_toggle=12.500000
junction_temp=25.4 (C) logic=0.003790 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.086519 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=csg324 pct_clock_constrained=7.000000 pct_inputs_defined=14 platform=nt64
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.012254 simulation_file=None
speedgrade=-1L static_prob=False temp_grade=industrial thetajb=6.8 (C/W)
thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=4.8
user_junc_temp=25.4 (C) user_thetajb=6.8 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000
vccadc_static_current=0.018000 vccadc_total_current=0.018000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000064
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.011355 vccaux_total_current=0.011419 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000468
vccbram_static_current=0.000279 vccbram_total_current=0.000746 vccbram_voltage=0.950000 vccint_dynamic_current=0.023301
vccint_static_current=0.006107 vccint_total_current=0.029408 vccint_voltage=0.950000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000491
vcco33_static_current=0.001000 vcco33_total_current=0.001491 vcco33_voltage=3.300000 version=2019.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=15.5 block_ram_tile_util_percentage=31.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=1 ramb18_util_percentage=1.00
ramb18e1_only_used=1 ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=15
ramb36_fifo_util_percentage=30.00 ramb36e1_only_used=15
primitives
bufg_functional_category=Clock bufg_used=2 carry4_functional_category=CarryLogic carry4_used=92
fdce_functional_category=Flop & Latch fdce_used=16 fdre_functional_category=Flop & Latch fdre_used=1308
fdse_functional_category=Flop & Latch fdse_used=16 ibuf_functional_category=IO ibuf_used=7
lut1_functional_category=LUT lut1_used=129 lut2_functional_category=LUT lut2_used=164
lut3_functional_category=LUT lut3_used=239 lut4_functional_category=LUT lut4_used=224
lut5_functional_category=LUT lut5_used=245 lut6_functional_category=LUT lut6_used=1990
muxf7_functional_category=MuxFx muxf7_used=616 muxf8_functional_category=MuxFx muxf8_used=305
obuf_functional_category=IO obuf_used=8 ramb18e1_functional_category=Block Memory ramb18e1_used=1
ramb36e1_functional_category=Block Memory ramb36e1_used=15 ramd32_functional_category=Distributed Memory ramd32_used=16
ramd64e_functional_category=Distributed Memory ramd64e_used=6144
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=616 f7_muxes_util_percentage=3.78
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=305 f8_muxes_util_percentage=3.74
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=6152 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=2725 lut_as_logic_util_percentage=13.10 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=6152 lut_as_memory_util_percentage=64.08 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=1340 register_as_flip_flop_util_percentage=3.22
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=8877 slice_luts_util_percentage=42.68
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=1340 slice_registers_util_percentage=3.22
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=6152 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=2725 lut_as_logic_util_percentage=13.10 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=6152 lut_as_memory_util_percentage=64.08 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=350 lut_in_front_of_the_register_is_used_fixed=350 lut_in_front_of_the_register_is_used_used=282
register_driven_from_outside_the_slice_fixed=282 register_driven_from_outside_the_slice_used=632 register_driven_from_within_the_slice_fixed=632 register_driven_from_within_the_slice_used=708
slice_available=8150 slice_fixed=0 slice_registers_available=41600 slice_registers_fixed=0
slice_registers_used=1340 slice_registers_util_percentage=3.22 slice_used=2612 slice_util_percentage=32.05
slicel_fixed=0 slicel_used=1066 slicem_fixed=0 slicem_used=1546
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_used=585 unique_control_sets_util_percentage=7.18
using_o5_and_o6_fixed=7.18 using_o5_and_o6_used=8 using_o5_output_only_fixed=8 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=6144
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35ticsg324-1L
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=candump_top -verilog_define=default::[not_specified]
usage
elapsed=00:01:05s hls_ip=2 memory_gain=698.063MB memory_peak=996.777MB