Design Name | rpc |
Device, Speed (SpeedFile Version) | XC9572XL, -10 (3.0) |
Date Created | Fri Sep 09 19:11:03 2011 |
Created By | Timing Report Generator: version H.42 |
Copyright | Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
---|
Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
---|---|
Min. Clock Period | 16.500 ns. |
Max. Clock Frequency (fSYSTEM) | 60.606 MHz. |
Limited by Cycle Time for CLK | |
Clock to Setup (tCYC) | 16.500 ns. |
Pad to Pad Delay (tPD) | 20.000 ns. |
Setup to Clock at the Pad (tSU) | 13.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 14.500 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
TS1001 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 16.5 | 250 | 250 |
AUTO_TS_P2P | 0.0 | 20.0 | 19 | 19 |
AUTO_TS_P2F | 0.0 | 14.8 | 39 | 39 |
AUTO_TS_F2P | 0.0 | 12.7 | 11 | 11 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
DIR.Q to DIR.D | 0.000 | 16.500 | -16.500 |
DIR.Q to U2/TSD.D | 0.000 | 16.500 | -16.500 |
EDG.Q to EDG.D | 0.000 | 16.500 | -16.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
SD to FB | 0.000 | 20.000 | -20.000 |
CLK to FB | 0.000 | 14.500 | -14.500 |
CLK to SD | 0.000 | 14.500 | -14.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
A to DIR.D | 0.000 | 14.800 | -14.800 |
A to EDG.D | 0.000 | 14.800 | -14.800 |
B to DIR.D | 0.000 | 14.800 | -14.800 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
OE.Q to FB | 0.000 | 12.700 | -12.700 |
OE.Q to SD | 0.000 | 12.700 | -12.700 |
SD.Q to SD | 0.000 | 8.500 | -8.500 |
Clock | fEXT (MHz) | Reason |
---|---|---|
MCK | 111.111 | Limited by Clock Pulse Width for MCK |
CLK | 60.606 | Limited by Cycle Time for CLK |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
CS | 6.500 | 0.000 |
DIN<0> | 12.000 | 0.000 |
DIN<1> | 12.000 | 0.000 |
DIN<2> | 12.000 | 0.000 |
DIN<3> | 12.000 | 0.000 |
DIN<4> | 12.000 | 0.000 |
DIN<5> | 12.000 | 0.000 |
DIN<6> | 12.000 | 0.000 |
DIN<7> | 12.000 | 0.000 |
WR | 6.500 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
A | 13.000 | 0.000 |
B | 13.000 | 0.000 |
MODE | 13.000 | 0.000 |
SD | 12.000 | 0.000 |
STP | 12.000 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FB | 14.500 |
SD | 14.500 |
DIR | 5.800 |
DOUT<0> | 5.800 |
DOUT<1> | 5.800 |
DOUT<2> | 5.800 |
DOUT<3> | 5.800 |
EDG | 5.800 |
OE | 5.800 |
SCK | 5.800 |
Source | Destination | Delay |
---|---|---|
DIR.Q | DIR.D | 16.500 |
DIR.Q | U2/TSD.D | 16.500 |
EDG.Q | EDG.D | 16.500 |
SCIS<0>.Q | U2/TSD.D | 16.500 |
SCIS<1>.Q | U2/TSD.D | 16.500 |
SCIS<2>.Q | U2/TSD.D | 16.500 |
SCIS<3>.Q | U2/TSD.D | 16.500 |
SCIS<4>.Q | U2/TSD.D | 16.500 |
SCK.Q | DIR.D | 16.500 |
SCK.Q | U1/TMR<0>.D | 16.500 |
SCKX<0>.Q | DIR.D | 16.500 |
SCKX<0>.Q | U1/TMR<0>.D | 16.500 |
SCKX<1>.Q | DIR.D | 16.500 |
SCKX<1>.Q | U1/TMR<0>.D | 16.500 |
U1/MSP.Q | U1/TMR<0>.D | 16.500 |
U1/TMR<0>.Q | U1/TMR<0>.D | 16.500 |
U1/TMR<4>.Q | U1/TMR<0>.D | 16.500 |
U1/TMR<4>.Q | U2/TSD.D | 16.500 |
U1/TMR<5>.Q | U2/TSD.D | 16.500 |
U4/C.Q | DIR.D | 16.500 |
U4/C.Q | EDG.D | 16.500 |
U4/Q.Q | DIR.D | 16.500 |
EDG.Q | U1/MSP.D | 15.500 |
EDG.Q | U4/C.D | 15.500 |
SCIS<0>.Q | OE.D | 15.500 |
SCIS<0>.Q | SCIS<0>.D | 15.500 |
SCIS<0>.Q | SCIS<1>.D | 15.500 |
SCIS<0>.Q | SCIS<2>.D | 15.500 |
SCIS<0>.Q | SCIS<3>.D | 15.500 |
SCIS<0>.Q | SCIS<4>.D | 15.500 |
SCIS<0>.Q | SD.D | 15.500 |
SCIS<0>.Q | U3/RDR<0>.D | 15.500 |
SCIS<0>.Q | U3/RDR<1>.D | 15.500 |
SCIS<0>.Q | U3/RDR<2>.D | 15.500 |
SCIS<0>.Q | U3/RDR<3>.D | 15.500 |
SCIS<1>.Q | OE.D | 15.500 |
SCIS<1>.Q | SCIS<1>.D | 15.500 |
SCIS<1>.Q | SCIS<2>.D | 15.500 |
SCIS<1>.Q | SCIS<3>.D | 15.500 |
SCIS<1>.Q | SCIS<4>.D | 15.500 |
SCIS<1>.Q | SD.D | 15.500 |
SCIS<1>.Q | U3/RDR<0>.D | 15.500 |
SCIS<1>.Q | U3/RDR<1>.D | 15.500 |
SCIS<1>.Q | U3/RDR<2>.D | 15.500 |
SCIS<1>.Q | U3/RDR<3>.D | 15.500 |
SCIS<2>.Q | OE.D | 15.500 |
SCIS<2>.Q | SCIS<2>.D | 15.500 |
SCIS<2>.Q | SCIS<3>.D | 15.500 |
SCIS<2>.Q | SCIS<4>.D | 15.500 |
SCIS<2>.Q | SD.D | 15.500 |
SCIS<2>.Q | U3/RDR<0>.D | 15.500 |
SCIS<2>.Q | U3/RDR<1>.D | 15.500 |
SCIS<2>.Q | U3/RDR<2>.D | 15.500 |
SCIS<2>.Q | U3/RDR<3>.D | 15.500 |
SCIS<3>.Q | OE.D | 15.500 |
SCIS<3>.Q | SCIS<3>.D | 15.500 |
SCIS<3>.Q | SCIS<4>.D | 15.500 |
SCIS<3>.Q | SD.D | 15.500 |
SCIS<3>.Q | U3/RDR<0>.D | 15.500 |
SCIS<3>.Q | U3/RDR<1>.D | 15.500 |
SCIS<3>.Q | U3/RDR<2>.D | 15.500 |
SCIS<3>.Q | U3/RDR<3>.D | 15.500 |
SCIS<4>.Q | OE.D | 15.500 |
SCIS<4>.Q | SCIS<0>.D | 15.500 |
SCIS<4>.Q | SCIS<1>.D | 15.500 |
SCIS<4>.Q | SCIS<2>.D | 15.500 |
SCIS<4>.Q | SCIS<3>.D | 15.500 |
SCIS<4>.Q | SCIS<4>.D | 15.500 |
SCIS<4>.Q | SD.D | 15.500 |
SCIS<4>.Q | U3/RDR<0>.D | 15.500 |
SCIS<4>.Q | U3/RDR<1>.D | 15.500 |
SCIS<4>.Q | U3/RDR<2>.D | 15.500 |
SCIS<4>.Q | U3/RDR<3>.D | 15.500 |
SCK.Q | OE.D | 15.500 |
SCK.Q | SCIS<0>.D | 15.500 |
SCK.Q | SCIS<1>.D | 15.500 |
SCK.Q | SCIS<2>.D | 15.500 |
SCK.Q | SCIS<3>.D | 15.500 |
SCK.Q | SCIS<4>.D | 15.500 |
SCK.Q | SCK.D | 15.500 |
SCK.Q | SCKX<0>.D | 15.500 |
SCK.Q | SCKX<1>.D | 15.500 |
SCK.Q | SD.D | 15.500 |
SCK.Q | U1/TMR<1>.D | 15.500 |
SCK.Q | U1/TMR<2>.D | 15.500 |
SCK.Q | U1/TMR<3>.D | 15.500 |
SCK.Q | U1/TMR<4>.D | 15.500 |
SCK.Q | U1/TMR<5>.D | 15.500 |
SCKX<0>.Q | OE.D | 15.500 |
SCKX<0>.Q | SCIS<0>.D | 15.500 |
SCKX<0>.Q | SCIS<1>.D | 15.500 |
SCKX<0>.Q | SCIS<2>.D | 15.500 |
SCKX<0>.Q | SCIS<3>.D | 15.500 |
SCKX<0>.Q | SCIS<4>.D | 15.500 |
SCKX<0>.Q | SCK.D | 15.500 |
SCKX<0>.Q | SCKX<0>.D | 15.500 |
SCKX<0>.Q | SCKX<1>.D | 15.500 |
SCKX<0>.Q | SD.D | 15.500 |
SCKX<0>.Q | U1/TMR<1>.D | 15.500 |
SCKX<0>.Q | U1/TMR<2>.D | 15.500 |
SCKX<0>.Q | U1/TMR<3>.D | 15.500 |
SCKX<0>.Q | U1/TMR<4>.D | 15.500 |
SCKX<0>.Q | U1/TMR<5>.D | 15.500 |
SCKX<1>.Q | OE.D | 15.500 |
SCKX<1>.Q | SCIS<0>.D | 15.500 |
SCKX<1>.Q | SCIS<1>.D | 15.500 |
SCKX<1>.Q | SCIS<2>.D | 15.500 |
SCKX<1>.Q | SCIS<3>.D | 15.500 |
SCKX<1>.Q | SCIS<4>.D | 15.500 |
SCKX<1>.Q | SCK.D | 15.500 |
SCKX<1>.Q | SCKX<0>.D | 15.500 |
SCKX<1>.Q | SCKX<1>.D | 15.500 |
SCKX<1>.Q | SD.D | 15.500 |
SCKX<1>.Q | U1/TMR<1>.D | 15.500 |
SCKX<1>.Q | U1/TMR<2>.D | 15.500 |
SCKX<1>.Q | U1/TMR<3>.D | 15.500 |
SCKX<1>.Q | U1/TMR<4>.D | 15.500 |
SCKX<1>.Q | U1/TMR<5>.D | 15.500 |
SD.Q | SD.D | 15.500 |
U1/MSP.Q | U1/TMR<1>.D | 15.500 |
U1/MSP.Q | U1/TMR<2>.D | 15.500 |
U1/MSP.Q | U1/TMR<3>.D | 15.500 |
U1/MSP.Q | U1/TMR<4>.D | 15.500 |
U1/MSP.Q | U1/TMR<5>.D | 15.500 |
U1/TMR<0>.Q | U1/TMR<1>.D | 15.500 |
U1/TMR<0>.Q | U1/TMR<2>.D | 15.500 |
U1/TMR<0>.Q | U1/TMR<3>.D | 15.500 |
U1/TMR<0>.Q | U1/TMR<4>.D | 15.500 |
U1/TMR<0>.Q | U1/TMR<5>.D | 15.500 |
U1/TMR<1>.Q | U1/TMR<1>.D | 15.500 |
U1/TMR<1>.Q | U1/TMR<2>.D | 15.500 |
U1/TMR<1>.Q | U1/TMR<3>.D | 15.500 |
U1/TMR<1>.Q | U1/TMR<4>.D | 15.500 |
U1/TMR<1>.Q | U1/TMR<5>.D | 15.500 |
U1/TMR<2>.Q | U1/TMR<2>.D | 15.500 |
U1/TMR<2>.Q | U1/TMR<3>.D | 15.500 |
U1/TMR<2>.Q | U1/TMR<4>.D | 15.500 |
U1/TMR<2>.Q | U1/TMR<5>.D | 15.500 |
U1/TMR<3>.Q | U1/TMR<3>.D | 15.500 |
U1/TMR<3>.Q | U1/TMR<4>.D | 15.500 |
U1/TMR<3>.Q | U1/TMR<5>.D | 15.500 |
U1/TMR<4>.Q | SCIS<0>.D | 15.500 |
U1/TMR<4>.Q | SCIS<1>.D | 15.500 |
U1/TMR<4>.Q | SCIS<2>.D | 15.500 |
U1/TMR<4>.Q | SCIS<3>.D | 15.500 |
U1/TMR<4>.Q | SCIS<4>.D | 15.500 |
U1/TMR<4>.Q | U1/TMR<1>.D | 15.500 |
U1/TMR<4>.Q | U1/TMR<2>.D | 15.500 |
U1/TMR<4>.Q | U1/TMR<3>.D | 15.500 |
U1/TMR<4>.Q | U1/TMR<4>.D | 15.500 |
U1/TMR<4>.Q | U1/TMR<5>.D | 15.500 |
U1/TMR<5>.Q | SCIS<0>.D | 15.500 |
U1/TMR<5>.Q | SCIS<1>.D | 15.500 |
U1/TMR<5>.Q | SCIS<2>.D | 15.500 |
U1/TMR<5>.Q | SCIS<3>.D | 15.500 |
U1/TMR<5>.Q | SCIS<4>.D | 15.500 |
U1/TMR<5>.Q | U1/TMR<0>.D | 15.500 |
U1/TMR<5>.Q | U1/TMR<1>.D | 15.500 |
U1/TMR<5>.Q | U1/TMR<2>.D | 15.500 |
U1/TMR<5>.Q | U1/TMR<3>.D | 15.500 |
U1/TMR<5>.Q | U1/TMR<4>.D | 15.500 |
U1/TMR<5>.Q | U1/TMR<5>.D | 15.500 |
U2/TSD.Q | SD.D | 15.500 |
U3/RDR<0>.Q | DOUT<0>.D | 15.500 |
U3/RDR<0>.Q | U3/RDR<0>.D | 15.500 |
U3/RDR<1>.Q | DOUT<1>.D | 15.500 |
U3/RDR<1>.Q | U3/RDR<1>.D | 15.500 |
U3/RDR<2>.Q | DOUT<2>.D | 15.500 |
U3/RDR<2>.Q | U3/RDR<2>.D | 15.500 |
U3/RDR<3>.Q | DOUT<3>.D | 15.500 |
U3/RDR<3>.Q | U3/RDR<3>.D | 15.500 |
U3/RSD.Q | U3/RDR<0>.D | 15.500 |
U3/RSD.Q | U3/RDR<1>.D | 15.500 |
U3/RSD.Q | U3/RDR<2>.D | 15.500 |
U3/RSD.Q | U3/RDR<3>.D | 15.500 |
U3/SSD.Q | U3/RSD.D | 15.500 |
U4/C.Q | U4/C.D | 15.500 |
SCIS<0>.Q | DOUT<0>.CE | 10.000 |
SCIS<0>.Q | DOUT<1>.CE | 10.000 |
SCIS<0>.Q | DOUT<2>.CE | 10.000 |
SCIS<0>.Q | DOUT<3>.CE | 10.000 |
SCIS<1>.Q | DOUT<0>.CE | 10.000 |
SCIS<1>.Q | DOUT<1>.CE | 10.000 |
SCIS<1>.Q | DOUT<2>.CE | 10.000 |
SCIS<1>.Q | DOUT<3>.CE | 10.000 |
SCIS<2>.Q | DOUT<0>.CE | 10.000 |
SCIS<2>.Q | DOUT<1>.CE | 10.000 |
SCIS<2>.Q | DOUT<2>.CE | 10.000 |
SCIS<2>.Q | DOUT<3>.CE | 10.000 |
SCIS<3>.Q | DOUT<0>.CE | 10.000 |
SCIS<3>.Q | DOUT<1>.CE | 10.000 |
SCIS<3>.Q | DOUT<2>.CE | 10.000 |
SCIS<3>.Q | DOUT<3>.CE | 10.000 |
SCIS<4>.Q | DOUT<0>.CE | 10.000 |
SCIS<4>.Q | DOUT<1>.CE | 10.000 |
SCIS<4>.Q | DOUT<2>.CE | 10.000 |
SCIS<4>.Q | DOUT<3>.CE | 10.000 |
SCK.Q | DOUT<0>.CE | 10.000 |
SCK.Q | DOUT<1>.CE | 10.000 |
SCK.Q | DOUT<2>.CE | 10.000 |
SCK.Q | DOUT<3>.CE | 10.000 |
SCK.Q | EDG.CE | 10.000 |
SCK.Q | U1/MSP.CE | 10.000 |
SCK.Q | U2/TSD.CE | 10.000 |
SCK.Q | U3/RDR<0>.CE | 10.000 |
SCK.Q | U3/RDR<1>.CE | 10.000 |
SCK.Q | U3/RDR<2>.CE | 10.000 |
SCK.Q | U3/RDR<3>.CE | 10.000 |
SCK.Q | U3/RSD.CE | 10.000 |
SCK.Q | U3/SSD.CE | 10.000 |
SCK.Q | U4/C.CE | 10.000 |
SCK.Q | U4/Q.CE | 10.000 |
SCKX<0>.Q | DOUT<0>.CE | 10.000 |
SCKX<0>.Q | DOUT<1>.CE | 10.000 |
SCKX<0>.Q | DOUT<2>.CE | 10.000 |
SCKX<0>.Q | DOUT<3>.CE | 10.000 |
SCKX<0>.Q | EDG.CE | 10.000 |
SCKX<0>.Q | U1/MSP.CE | 10.000 |
SCKX<0>.Q | U2/TSD.CE | 10.000 |
SCKX<0>.Q | U3/RDR<0>.CE | 10.000 |
SCKX<0>.Q | U3/RDR<1>.CE | 10.000 |
SCKX<0>.Q | U3/RDR<2>.CE | 10.000 |
SCKX<0>.Q | U3/RDR<3>.CE | 10.000 |
SCKX<0>.Q | U3/RSD.CE | 10.000 |
SCKX<0>.Q | U3/SSD.CE | 10.000 |
SCKX<0>.Q | U4/C.CE | 10.000 |
SCKX<0>.Q | U4/Q.CE | 10.000 |
SCKX<1>.Q | DOUT<0>.CE | 10.000 |
SCKX<1>.Q | DOUT<1>.CE | 10.000 |
SCKX<1>.Q | DOUT<2>.CE | 10.000 |
SCKX<1>.Q | DOUT<3>.CE | 10.000 |
SCKX<1>.Q | EDG.CE | 10.000 |
SCKX<1>.Q | U1/MSP.CE | 10.000 |
SCKX<1>.Q | U2/TSD.CE | 10.000 |
SCKX<1>.Q | U3/RDR<0>.CE | 10.000 |
SCKX<1>.Q | U3/RDR<1>.CE | 10.000 |
SCKX<1>.Q | U3/RDR<2>.CE | 10.000 |
SCKX<1>.Q | U3/RDR<3>.CE | 10.000 |
SCKX<1>.Q | U3/RSD.CE | 10.000 |
SCKX<1>.Q | U3/SSD.CE | 10.000 |
SCKX<1>.Q | U4/C.CE | 10.000 |
SCKX<1>.Q | U4/Q.CE | 10.000 |
Source Pad | Destination Pad | Delay |
---|---|---|
SD | FB | 20.000 |
CS | DOUT<0> | 11.000 |
CS | DOUT<1> | 11.000 |
CS | DOUT<2> | 11.000 |
CS | DOUT<3> | 11.000 |
RD | DOUT<0> | 11.000 |
RD | DOUT<1> | 11.000 |
RD | DOUT<2> | 11.000 |
RD | DOUT<3> | 11.000 |